Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various building blocks (the
integrated block for PCI Express, the transceivers, block RAM, and clocking resources) into an Endpoint or Root Port
solution. The system designer has control over many configurable parameters: lane width, maximum payload size, PL
interface speeds, reference clock frequency, and base address register decoding and filtering. |
